1. Field of the Invention
The present invention relates to a ferroelectric memory device, and more specifically, to an effective arrangement of cell arrays and control circuits to improve the integration of a chip and minimize delay factors of signals.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as xe2x80x98FRAMxe2x80x99) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a DRAM (Dynamic Random Access Memory) and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance. As shown in FIG. 1, a polarization induced by an electric field does not vanish but keeps some strength (xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states may be assigned to binary values of xe2x80x981xe2x80x99and xe2x80x980xe2x80x99 for use as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device. As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC1 having the first terminal of the two terminals connected to the drain terminal of the transistor T1 and the second terminal of the two terminals connected to the plateline PL.
FIG. 3a is a timing diagram illustrating a write mode of the conventional FRAM.
Referring to FIG. 3a, when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d level, thereby selecting the cell.
In order to write a binary logic value xe2x80x9c1xe2x80x9d in the selected cell, a xe2x80x9chighxe2x80x9d signal is applied to a bitline BL while a xe2x80x9clowxe2x80x9d signal is applied to a plateline PL. In order to write a binary logic value xe2x80x9c0xe2x80x9d in the cell, a xe2x80x9clowxe2x80x9d signal is applied to a bitline BL while a xe2x80x9chighxe2x80x9d signal is applied to a plateline PL.
FIG. 3b is a timing diagram illustrating a read mode of the conventional FRAM. Referring to FIG. 3b, when a chip enable signal CSBpad externally transits from a xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d level, all bitlines are equalized to a xe2x80x9clowxe2x80x9d level by an equalization signal before selection of a required wordline.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d level, thereby selecting a corresponding unit cell. A xe2x80x9chighxe2x80x9d signal is applied to a plateline of the selected cell to cancel a data Qs corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the FRAM. If the logic value xe2x80x9c0xe2x80x9d is stored in the FRAM, a corresponding data Qns will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. In other words, as shown in the hysteresis loop of FIG. 1, the state moves from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 when the data is destroyed while the state moves from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 when the data is not destroyed.
As a result, the destroyed data amplified by the enabled sense amplifier outputs a logic value xe2x80x9c1xe2x80x9d while the non-destroyed data amplified by the sense amplifier outputs a logic value xe2x80x9c0xe2x80x9d. The original data is destroyed after the sense amplifier amplifies the data. Accordingly, when a xe2x80x9chighxe2x80x9d signal is applied to the required wordline, the plateline is disabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d, thereby recovering the original data.
Cell arrays and control circuits should be effectively arranged to embody a highly integrated FRAM operating at a high speed.
Accordingly, it is a first object of the present invention to maximize the efficiency of a layout by arranging adjacent circuits such as a pad array, a sense amplifier array and an address buffer in a center of symmetry of a cell array block, and symmetrically arranging data bus units perpendicular to the other center of symmetry of the cell array block.
It is a second object of the present invention to allow data to be effectively restored and written in the FRAM by controlling a sense amplifier using a column selection signal.
It is a third object of the present invention to supply a VPP to each cell array block at a high speed by dividing VPP-related circuits involved in the cell operation into a gate control-related VPP circuit of a small capacity and a VPP pump circuit of a large capacity, and effectively arranging them.
It is a fourth object of the present invention to provide a layout of a connection portion between the data bus unit and the cell array block, which increases process margin and signal transmission efficiency and minimizes a required area.
There is provided a ferroelectric memory device, comprises a cell array block, a data bus unit and a control circuit unit. The cell array block has a bitline structure including a main bitline and a plurlaity of sub bitlines. The main bitline is connected to a column selection controller, and the plurality of sub-bitlines have both terminals connected to the main bitline, respectively, and connected to a plurality of unit cells. The data bus unit is connected to the column selection controller. The control circuit unit includes a sense amplifier array connected between a data I/O buffer and a sense amplifier data bus connected to the data bus unit. A plurality of the cell array blocks are arranged like a matrix. The control circuit unit is disposed in a first center line of symmetry wherein the first center line is parallel to the main bitline, and the data bus unit is disposed in a second center line of symmetry wherein the second center line is vertical to the main bitline.